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S6C1108
6 BIT 384 CHANNEL RSDS TFT-LCD SOURCE DRIVER
Nov. 2002. Ver. 0.2
S6C1108
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
INTRODUCTION
The S6C1108 is a Source Driver suitable for Reduced Swing Differential Signaling(RSDS) digital interface. It converts 18-bit digital data into the analog voltage for 384 channels, charging each sub-pixel to the correct gray level corresponding to the digital value. The RSDS path to the panel timing controller contributes toward lowering radiated EMI, reducing system power consumption and eliminates one of the two pixel busses used in typical XGA, SXGA TFT LCD panels. This single 9-bit differential bus conveys the 18-bit color data for XGA, SXGA panels.
FEATURES
* * * * * * * * * * * * * * TFT active matrix LCD source driver LSI 64G/S is possible through 14(7 by 2) external power supply and D/A converter Both dot inversion display and N-line inversion display are possible Compatible with gamma-correction Charge sharing function Logic supply voltage[VDD1] : 2.7 to 3.6 V LCD driver supply voltage[VDD2] : 7.0 to 12.0 V Output dynamic range: VSS2+0.2V to VDD2-0.2V Maximum operating frequency: fmax=85 MHz (internal data transmission rate at 2.7 V operation) Output: 384 outputs Reduced Swing Differential Signaling(RSDS) interface for low power consumption and low EMI. Minimum RSDS input swing level(CLKP, CLKN, DATAP, DATAN): 100mV Data bus interface control pin (DATPOL) TCP or COF supported
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6 BIT 384 CHANNEL RSDS SOURCE DRIVER
S6C1108
BLOCK DIAGRAM
Y382 Y383 6 Y384 6
Y1 POL
Y2
Y3
Output Buffer
VGMA1 to VGMA14
14
R-DAC
6
6
6
6
CLK1
Data Latches
6
D00P D00N D01P D01N D22P D22N DATPOL CLKP CLKN
RSDS Receiver
Data Register
6 6 6
6 6
128 bit Shift Register
DIO1
SHL
DIO2
Figure 1. S6C1108 Block Diagram
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S6C1108
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
PIN ASSIGNMENTS
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 TESTI1 TESTO1 DIO1 D00N D00P D01N D01P D02N D02P DATPOL POL CLK1 CLKN CLKP VSS1 VGMA1 VGMA2 VGMA3 VGMA4 VGMA5 VGMA6 VGMA7 VSS2 VDD2 VGMA8 VGMA9 VGMA10 VGMA11 VGMA12 VGMA13 VGMA14 SHL VDD1 D10N D10P D11N D11P D12N D12P D20N D20P D21N D21P D22N D22P DIO2 TESTO2 TESTI2
Y372 Y373 Y374 Y375 Y376 Y377 Y378 Y379 Y380 Y381 Y382 Y383 Y384
Output 384
S6C1108
Input 48
Figure 2. S6C1108 Pin Assignments
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6 BIT 384 CHANNEL RSDS SOURCE DRIVER
S6C1108
PIN DESCRIPTIONS
Symbol VDD1 VDD2 VSS1 VSS2 Y1 to Y384 D0P<0:2> D0N<0:2> D1P<0:2> D1N<0:2> D2P<0:2> D2N<0:2> SHL DIO1 DIO2 DATPOL Pin Name Logic power supply Driver power supply Logic ground Driver ground Driver outputs 2.7 to 3.6 V 7.0 to 12.0 V Ground (0 V) Ground (0 V) The D/A converted 64 gray-scale analog voltage is output. Total data lines consist of 18 data bus. (6-bit digital, 3 colors(R, G, B) and 2 differential input pairs) The 3-bit differential input pairs generate the internal 6-bit data through the comparison between DxxP and DxxN. This pin controls the direction of shift register in cascade connection. When SHL=H: DIO1 input, Y1Y384, DIO2 output When SHL=L: DIO2 input, Y384Y1, DIO1 output SHL=H: Used as the start pulse input pin. SHL=L: Used as the start pulse output pin. SHL=H: Used as the start pulse output pin. SHL=L: Used as the start pulse input pin. DATPOL= L: No inversion DATPOL= H: Data polarity inversion ( DATPOL must be fixed VSS1 or VDD1.) POL=H: The reference voltage for odd number outputs are VGMA1 to VGMA7 and those for even number outputs are VGMA8 to VGMA14. POL=L: The reference voltage for odd number outputs are VGMA8 to VGMA14 and those for even number outputs are VGMA1 to VGMA7. The RSDS clock input pairs generate the internal shift clock, CLK2, through the comparison between CLKP and CLKN. S6C1108 clears 128 shift registers at the rising edge of CLK1 and outputs the analog data to the each channel at the falling edge. Description
RSDS data input
Shift direction control input Start pulse input/output Start pulse input/output Data inversion input
POL CLKP CLKN CLK1 VGMA1 to VGMA14 TESTI1/O1, TESTI2/O2
Polarity input
RSDS shift clock input Latch input
Input the gamma corrected power supplies from external source. Gamma corrected power VDD2>VGMA1>VGMA2>......>VGMA13>VGMA14>VSS2 supplies Keep power supplies unchanged during the gray-scale voltage output. Amp test input/output These pins are used for Amp test. TESTI1(=TESTI2)=L : Normal operation mode
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S6C1108
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
OPERATION DESCRIPTION
RSDS RECEIVER AND DEMUX The S6C1108 adapts the RSDS interface for EMI solution. The internal RSDS receiver block operates the comparison between the transmitted differential input pair data. The input data lines from the timing controller to the RSDS receiver consist of 6-bit digital, 3 colors, 1 port, 2 differential pairs(DxxP/DxxN). The input common mode voltage range at the RSDS receiver is 1.2V. The differential data and clock signals from the panel timing controller arrive at the S6C1108 as multiplexed, even and odd data fields. (i.e., the data is 2:1 multiplexed). The nominal peak to peak swing of this data is 200mV across a termination resistor.
RSDS DATA BUS INTERFACE CONTROL DATPOL controls the internal data inversion. When DATPOL="H", the internal data is inverted. The inverted data is the same that the RSDS receiver operates the comparison between the cross-transmitted differential input pair data. Using the data inversion input pin, DATPOL, the RSDS data bus interface can be changed.
DISPLAY DATA TRANSFER When DIO1 (or DIO2) pulse is loaded into the internal latch on the falling edge of CLKP, DIO1 (or DIO2) pulse enables the operation of data transfer, so display data is valid on the 2nd falling edge of CLKP. Once all the data of 384 channels is loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLKP is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the 2nd falling edge of CLKP after the rising edge of DIO1 (or DIO2).
EXTENSION OF OUTPUT Output pin can be adjusted to an extended screen by cascade connection. When SHL="L", Connect DIO1 pin of the previous stage to the DIO2 pin of the next stage and all the input pins except DIO1 and DIO2 are connected together in each device. When SHL="H", Connect DIO2 pin of the previous stage to the DIO1 pin of the next stage and all the input pins except DIO2 and DIO1 are connected together in each device.
RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE The LCD drive output voltages are determined by the input data and 14 (7 by 2) gamma corrected power supplies (VGMA1 to VGMA14). Besides, to be able to deal with dot line inversion when mounted on a singleside, gradation voltages with different polarity can be output to the odd number output pins and the even number output pins. Among 7-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity with respect to the common voltage, for the respective 7 gamma corrected voltages of VGMA1 to VGMA7 and VGMA8 to VGMA14.
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6 BIT 384 CHANNEL RSDS SOURCE DRIVER
S6C1108
VDD2 VGMA1 VGMA2 VGMA3 VGMA4 VGMA5 VGMA6 VGMA7 VCOM VGMA8 VGMA9 VGMA10 VGMA11 VGMA12 VGMA13 VGMA14 VSS2 00H 08H 10H 18H 20H 28H 30H 38H 3FH Input data
Figure 3. Gamma Correction Curve
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S6C1108
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
Table 1. Resistor Strings (R0 to R62, unit: ) Name R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Value 2008 1307 958 731 606 507 431 373 328 292 263 243 226 209 195 181 Name R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 Value 169 156 149 140 133 126 122 119 115 112 108 104 101 97 94 90 Name R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 Value 88 86 84 83 81 81 81 81 81 81 81 81 81 83 84 84 Total R :
IC internal circuits
VGMA1 VGMA2 VGMA3 R2_3 (6850) R3_4 (1935) R4_5 (1321) R5_6 (2201)
Name R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62
Value 85 88 92 97 103 110 118 126 136 152 187 234 289 384 508 14823
DATA
00H
The S6C1108 has on-chip dividing resistors. The gamma correction voltage input pins are divided into two parts. Each part is connected in series with resistors. Each of these resistor series has a total typical value of 14823. Note that since these voltages are resistor divided internally, the voltages applied to the VGMAn pins should be applied through a low-impedance circuit. If the voltages are directly applied by the resistor divider, the desired output voltages may not result (Recommend you to use operational amplifier).
External Gamma correction voltage generating circuit
VGMA4 VGMA5 VGMA6 VGMA7 VGMA8 VGMA9 VGMA10 VGMA11 VGMA12 VGMA13 VGMA14
3FH 3FH
R9_10 (2201) R10_11 (1321) R11_12 (1935) R12_13 (6850)
00H
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6 BIT 384 CHANNEL RSDS SOURCE DRIVER
S6C1108
Table 2. Relationship between Input Data and Output Voltage Value Input Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 G/S VH0 VH1 VH2 VH3 VH4 VH5 VH6 VH7 VH8 VH9 VH10 VH11 VH12 VH13 VH14 VH15 VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23 VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31 Output Voltage VGMA1 VGMA2 VGMA2+(VGMA3-VGMA2) x 1307/6850 VGMA2+(VGMA3-VGMA2) x 2265/6850 VGMA2+(VGMA3-VGMA2) x 2996/6850 VGMA2+(VGMA3-VGMA2) x 3602/6850 VGMA2+(VGMA3-VGMA2) x 4109/6850 VGMA2+(VGMA3-VGMA2) x 4540/6850 VGMA2+(VGMA3-VGMA2) x 4913/6850 VGMA2+(VGMA3-VGMA2) x 5241/6850 VGMA2+(VGMA3-VGMA2) x 5533/6850 VGMA2+(VGMA3-VGMA2) x 5796/6850 VGMA2+(VGMA3-VGMA2) x 6039/6850 VGMA2+(VGMA3-VGMA2) x 6265/6850 VGMA2+(VGMA3-VGMA2) x 6474/6850 VGMA2+(VGMA3-VGMA2) x 6669/6850 VGMA3 VGMA3+(VGMA4-VGMA3) x 169/1935 VGMA3+(VGMA4-VGMA3) x 325/1935 VGMA3+(VGMA4-VGMA3) x 474/1935 VGMA3+(VGMA4-VGMA3) x 614/1935 VGMA3+(VGMA4-VGMA3) x 747/1935 VGMA3+(VGMA4-VGMA3) x 873/1935 VGMA3+(VGMA4-VGMA3) x 995/1935 VGMA3+(VGMA4-VGMA3) x 1114/1935 VGMA3+(VGMA4-VGMA3) x 1229/1935 VGMA3+(VGMA4-VGMA3) x 1341/1935 VGMA3+(VGMA4-VGMA3) x 1449/1935 VGMA3+(VGMA4-VGMA3) x 1553/1935 VGMA3+(VGMA4-VGMA3) x 1654/1935 VGMA3+(VGMA4-VGMA3) x 1751/1935 VGMA3+(VGMA4-VGMA3) x 1845/1935
NOTE: VDD2>VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7
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S6C1108
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input Data 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 G/S VH32 VH33 VH34 VH35 VH36 VH37 VH38 VH39 VH40 VH41 VH42 VH43 VH44 VH45 VH46 VH47 VH48 VH49 VH50 VH51 VH52 VH53 VH54 VH55 VH56 VH57 VH58 VH59 VH60 VH61 VH62 VH63 Output Voltage VGMA4 VGMA4+(VGMA5-VGMA4) x 88/1321 VGMA4+(VGMA5-VGMA4) x 174/1321 VGMA4+(VGMA5-VGMA4) x 258/1321 VGMA4+(VGMA5-VGMA4) x 341/1321 VGMA4+(VGMA5-VGMA4) x 422/1321 VGMA4+(VGMA5-VGMA4) x 503/1321 VGMA4+(VGMA5-VGMA4) x 584/1321 VGMA4+(VGMA5-VGMA4) x 665/1321 VGMA4+(VGMA5-VGMA4) x 746/1321 VGMA4+(VGMA5-VGMA4) x 827/1321 VGMA4+(VGMA5-VGMA4) x 908/1321 VGMA4+(VGMA5-VGMA4) x 989/1321 VGMA4+(VGMA5-VGMA4) x 1070/1321 VGMA4+(VGMA5-VGMA4) x 1153/1321 VGMA4+(VGMA5-VGMA4) x 1237/1321 VGMA5 VGMA5+(VGMA6-VGMA5) x 85/2201 VGMA5+(VGMA6-VGMA5) x 173/2201 VGMA5+(VGMA6-VGMA5) x 265/2201 VGMA5+(VGMA6-VGMA5) x 362/2201 VGMA5+(VGMA6-VGMA5) x 465/2201 VGMA5+(VGMA6-VGMA5) x 575/2201 VGMA5+(VGMA6-VGMA5) x 693/2201 VGMA5+(VGMA6-VGMA5) x 819/2201 VGMA5+(VGMA6-VGMA5) x 955/2201 VGMA5+(VGMA6-VGMA5) x 1107/2201 VGMA5+(VGMA6-VGMA5) x 1294/2201 VGMA5+(VGMA6-VGMA5) x 1528/2201 VGMA5+(VGMA6-VGMA5) x 1817/2201 VGMA6 VGMA7
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6 BIT 384 CHANNEL RSDS SOURCE DRIVER
S6C1108
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 0 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 G/S VL0 VL1 VL2 VL3 VL4 VL5 VL6 VL7 VL8 VL9 VL10 VL11 VL12 VL13 VL14 VL15 VL16 VL17 VL18 VL19 VL20 VL21 VL22 VL23 VL24 VL25 VL26 VL27 VL28 VL29 VL30 VL31 Output Voltage VGMA14 VGMA13 VGMA13+(VGMA12-VGMA13) x 1307/6850 VGMA13+(VGMA12-VGMA13) x 2265/6850 VGMA13+(VGMA12-VGMA13) x 2996/6850 VGMA13+(VGMA12-VGMA13) x 3602/6850 VGMA13+(VGMA12-VGMA13) x 4109/6850 VGMA13+(VGMA12-VGMA13) x 4540/6850 VGMA13+(VGMA12-VGMA13) x 4913/6850 VGMA13+(VGMA12-VGMA13) x 5241/6850 VGMA13+(VGMA12-VGMA13) x 5533/6850 VGMA13+(VGMA12-VGMA13) x 5796/6850 VGMA13+(VGMA12-VGMA13) x 6039/6850 VGMA13+(VGMA12-VGMA13) x 6265/6850 VGMA13+(VGMA12-VGMA13) x 6474/6850 VGMA13+(VGMA12-VGMA13) x 6669/6850 VGMA12 VGMA12+(VGMA11-VGMA12) x 169/1935 VGMA12+(VGMA11-VGMA12) x 325/1935 VGMA12+(VGMA11-VGMA12) x 474/1935 VGMA12+(VGMA11-VGMA12) x 614/1935 VGMA12+(VGMA11-VGMA12) x 747/1935 VGMA12+(VGMA11-VGMA12) x 873/1935 VGMA12+(VGMA11-VGMA12) x 995/1935 VGMA12+(VGMA11-VGMA12) x 1114/1935 VGMA12+(VGMA11-VGMA12) x 1229/1935 VGMA12+(VGMA11-VGMA12) x 1341/1935 VGMA12+(VGMA11-VGMA12) x 1449/1935 VGMA12+(VGMA11-VGMA12) x 1553/1935 VGMA12+(VGMA11-VGMA12) x 1654/1935 VGMA12+(VGMA11-VGMA12) x 1751/1935 VGMA12+(VGMA11-VGMA12) x 1845/1935
NOTE: VGMA8>VGMA9>VGMA10>VGMA11>VGMA12> VGMA13>VGMA14>VSS2
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S6C1108
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input Data 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 G/S VL32 VL33 VL34 VL35 VL36 VL37 VL38 VL39 VL40 VL41 VL42 VL43 VL44 VL45 VL46 VL47 VL48 VL49 VL50 VL51 VL52 VL53 VL54 VL55 VL56 VL57 VL58 VL59 VL60 VL61 VL62 VL63 Output Voltage VGMA11 VGMA11+(VGMA10-VGMA11) x 88/1321 VGMA11+(VGMA10-VGMA11) x 174/1321 VGMA11+(VGMA10-VGMA11) x 258/1321 VGMA11+(VGMA10-VGMA11) x 341/1321 VGMA11+(VGMA10-VGMA11) x 422/1321 VGMA11+(VGMA10-VGMA11) x 503/1321 VGMA11+(VGMA10-VGMA11) x 584/1321 VGMA11+(VGMA10-VGMA11) x 665/1321 VGMA11+(VGMA10-VGMA11) x 746/1321 VGMA11+(VGMA10-VGMA11) x 827/1321 VGMA11+(VGMA10-VGMA11) x 908/1321 VGMA11+(VGMA10-VGMA11) x 989/1321 VGMA11+(VGMA10-VGMA11) x 1070/1321 VGMA11+(VGMA10-VGMA11) x 1153/1321 VGMA11+(VGMA10-VGMA11) x 1237/1321 VGMA10 VGMA10+(VGMA9-VGMA10) x 85/2201 VGMA10+(VGMA9-VGMA10) x 173/2201 VGMA10+(VGMA9-VGMA10) x 265/2201 VGMA10+(VGMA9-VGMA10) x 362/2201 VGMA10+(VGMA9-VGMA10) x 465/2201 VGMA10+(VGMA9-VGMA10) x 575/2201 VGMA10+(VGMA9-VGMA10) x 693/2201 VGMA10+(VGMA9-VGMA10) x 819/2201 VGMA10+(VGMA9-VGMA10) x 955/2201 VGMA10+(VGMA9-VGMA10) x 1107/2201 VGMA10+(VGMA9-VGMA10) x 1294/2201 VGMA10+(VGMA9-VGMA10) x 1528/2201 VGMA10+(VGMA9-VGMA10) x 1817/2201 VGMA9 VGMA8
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6 BIT 384 CHANNEL RSDS SOURCE DRIVER
S6C1108
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Input voltage Symbol VDD1 VDD2 VGMA1 to 14 TESTI1, TESTI2 Others Output voltage Operating power dissipation Operation temperature Storage temperature DIO1, DIO2 Y1 to Y384 Pd Top Tstg CAUTIONS: If LSIs are stressed beyond those listed above "absolute maximum ratings", they may be permanently destroyed. These are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Turn on power order: VDD1 control signal input VDD2 VGMA1 to VGMA14 Turn off power order: VGMA1 to VGMA14 VDD2 control signal input VDD1 Ratings -0.3 to 4.0 -0.3 to 13.0 -0.3 to VDD2 + 0.3 -0.3 to VDD2 + 0.3 -0.3 to VDD1 + 0.3 -0.3 to VDD1 + 0.3 -0.3 to VDD2 + 0.3 300 -20 to 75 -55 to 125 V mW C C V Unit V V
RECOMMENDED OPERATION CONDITIONS
Table 4. Recommended Operation Conditions (Ta = - 20 to 75 C, VSS1 = VSS2 = 0 V) Parameter Logic supply voltage Driver supply voltage Gamma corrected voltage Driver part output voltage Maximum clock frequency Output load capacitance VDD1 VDD2 VGMA1 to VGMA7 VGMA8 to VGMA14 Vyo fmax CL Symbol Min. 2.7 7.0 0.5VDD2 VSS2+ 0.2 VSS2+ 0.2 Typ. 3.0 10.0 Max. 3.6 12.0 VDD2 - 0.2 0.5VDD2 VDD2 - 0.2 85 150 Unit V V V V V MHz pF / PIN
VDD1 = 2.7V
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S6C1108
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
DC CHARACTERISTICS
Table 5 . DC Characteristics (Ta = -20 to 75 C, VDD1 = 2.7 to 3.6 V, VDD2 = 7.0 to 12.0 V, VSS1 = VSS2 = 0) Parameter High level input voltage Low level input voltage Input leakage current TESTI input leak current High level output voltage Low level output voltage Resistance between gamma voltage Symbol VIH VIL IL1 IL2 VOH VOL R0 to R62 IVOH1 Driver output current IVOL1 Condition SHL, CLK1, POL, DATPOL, DIO1 (DIO2) TESTI1(TESTI2) DIO1(DIO2), IO = - 1.0 mA DIO1(DIO2), IO = + 1.0 mA Refer to Table 1. Resistor Strings VDD2 = 10.0 V, Vx(1) = 5.0 V, Vyo(2) = 9.0 V VDD2 = 10.0 V, Vx = 5.0 V, Vyo = 1.0 V VDD2 = 10.0V Vyo = 1.5 V ~ 8.5 V DVrms(3) VDD2 = 10.0V Vyo = 0.2 V ~ 1.5 V Vyo = 8.5 V ~ 9.8 V VDD2 = 10.0V Vyo = 1.5 V ~ 8.5 V Dvo VDD2 = 10.0V Vyo = 0.2 V ~ 1.5 V Vyo = 8.5 V ~ 9.8 V VDD2 = 10.0V Dxx = 20H (32 G/S) Input data: 00H to 3FH VDD1 = 3.0 V (4) VDD2 = 10.0V Load condition 120pF(5)(6) VDD2 = 10.0V No load condition(5)(7) Min. 0.7VDD1 VSS1 -1 -1 VDD1 - 0.5 Rn x 0.7 0.4 VSS2 + 0.2 - 0.8 0.8 3 20 30 Typ. Max. VDD1 0.3VDD1 1 1 0.5 Rn x 1.3 - 0.4 mA 10 30 mV 30 7 VDD2 - 0.2 6 25 15 mA mV V Unit V A V
Output swing voltage difference deviation
Output pin voltage difference deviation
Output average voltage Output voltage range Logic part dynamic current Driver part dynamic current
AVo Vyo IDD1 IDD2 IDD3
NOTES: 1. Vx is the voltage applied to analog output pins Y1 to Y384. 2. Vyo is the output voltage of analog output pins Y1 to Y384. 3. dVrms = max. deviation of (VHx-VLx) VHx; the x gray level positive polarity driver output voltage VLx; the x gray level negative polarity driver output voltage 4. CLK1 period = 20.68 s raster cycle at fCLKP = 65 MHz, input data pattern = 1010......, (checkerboard pattern) alternating data pattern per CLKP, Ta = 25 C.
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6 BIT 384 CHANNEL RSDS SOURCE DRIVER
S6C1108
5. CLK1 period = 20.68 s raster cycle at fCLKP = 65 MHz, input data 00H fixed, alternating POL per raster cycle and VGMA1 = VDD2-0.2V, VGMA14 = VSS2 + 0.2V fixed, Ta = 25 C. 6. Yout load condition : 120pF(tester load). Refer to Figure 4. 7. Yout load condition : No load(Yout open). Refer to Figure 4.
VDD1 VDD2 IDD1 DUT A VDD1 Y1 Y2 120pF IDD2 IDD3 A VDD2 Y384 VSS2 VSS1
0V
Figure 4.
DUT : Device Under Test
Yout Load Condition(IDD2&3)
15
S6C1108
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
RSDS CHARACTERISTICS
Table 6 . RSDS Characteristics (Ta = - 20 to 75 C, VDD1 = 2.7 to 3.6 V, VDD2 = 7.0 to 12.0 V, VSS1 = VSS2 = 0) Parameter Symbol Condition Min. Typ. Max. RSDS high input voltage RSDS low input voltage RSDS common mode input voltage range RSDS input leakage current VIHRSDS VILRSDS VCMRSDS IDL VCMRSDS = + 1.1 V
(1)
Unit mV V A
100 0.9 - 10
200 - 200 -
- 100 1.3 10
VCMRSDS = + 1.1 V (1) VIHRSDS=+100 mV VILRSDS=-100mV (2) DxxP, DxxN, CLKP, CLKN
NOTES: 1. VCMRSDS = (VCLKP + VCLKN) / 2 or VCMRSDS = (VDxxP + VDxxN) / 2 2. The positive sign means that DxxP(or CLKP) is higher than RSDS ground DxxN(or CLKN). The negative sign means that DxxP(or CLKP) is lower than RSDS ground DxxN(or CLKN).
VRSDSN
VIHRSDS VILRSDS VCMRSDS
VRSDSP
GND
VIHRSDS
(VRSDSP)-(VRSDSN)
VILRSDS
0V
Figure 5. RSDS signal definition
16
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
S6C1108
AC CHARACTERISTICS
Table 7. AC Characteristics (Ta = - 20 to 75 C, VDD1 = 2.7 to 3.6 V, VDD2 = 7.0 to 12.0 V, VSS1 = VSS2 = 0 V) Parameter Clock pulse width Clock pulse low period Clock pulse high period Data setup time Data hold time Start pulse setup time Start pulse hold time Start pulse delay time DIO signal pulse width CLK1 setup time CLK1 high pulse width Driver output delay time1 Driver output delay time2 Last data timing CLK1-CLKP time POL-CLK1 time CLK1-POL time Symbol PWCLK PWCLK(L) PWCLK(H) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tPLH1 PWDIO tSETUP3 PWCLK1 tPHL1 tPHL2 tLDT tCLK1-CLKP tPOL-CLK1 tCLK1-POL (1) (1) (1) (1)
Condition
Min. 11.7 4 4 2 0 4 2 1CLKP 2CLKP 5CLKP 1CLKP 4 14 10
Typ. -
Max. 7.7 2CLKP 6 10 -
Unit
ns
CL = 15pF (2) (4) (3) (4)
CLKP period s CLKP period ns
CLK1 CLKP POL or CLK1 CLK1 POL or
NOTES: (1). VCMRSDS = +1.1V, VDIFFRSDS = VRSDSP - VRSDSN = 200mV (2). The value is specified when the drive voltage value reaches the target output voltage level of 90% (3). The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy. (4). Yout load condition (refer to Figure 6)
Measure Point Y1 Y2 10k 20k 20k
30pF
30pF
30pF
Y384
Figure 6. Yout load condition
17
18
PWCLK(L) PWCLK(H)
50% 50% 50% 50% 50%
S6C1108
CLKP-CLKN (RSDS)
PWCLK
Input
tPLH1 tLDT
WAVEFORMS
PWDIO
DIO1; SHL=H DIO2; SHL=L
10%
10%
DxxP-DxxN (RSDS) Invalid
EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD
Invalid
Output
70%
1st Data
2nd Data
DIO1; SHL=H DIO2; SHL=L
tCLK1- CLKP PWCLK1
70% 30% 70% 30%
CLK1
tPOL-CLK1
70% 30%
tCLK1-POL
70% 30% tPHL1 tPHL2 HZ 90%
Figure 7. Waveforms
50%
POL
Y1 to Y384
CLKP-CLKN
VIHRSDS 0V VILRSDS
CLKP-CLKN
50%
50%
VIHRSDS 0V VILRSDS
tHOLD1 tSETUP1
tSETUP2 tHOLD2
70%
tSETUP1 tHOLD1
Input
70%
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
DIO1; SHL=H DIO2; SHL=L
DxxP-DxxN
50%
50%
50%
VIHRSDS 0V VILRSDS
CLKP-CLKN (RSDS) PWCLK 0.5VDD1 1(CLKP-CLKN)
DIO1 input (DIO2 input)
CLK1
Min. 2(CLKP-CLKN)
tLDT
N-1th Nth DATA DATA
tSETUP3 INVALID DATA blanking time = Min. 4(CLKP-CLKN)
1st 2nd DATA DATA
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
DXXP-DXXN (RSDS)
Last data
First data in the next line
RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD
Figure 8. Waveforms
HI-Z HI-Z HI-Z VGMA8 - VGMA14 VGMA1 - VGMA7 VGMA1 - VGMA7 VGMA8 - VGMA14 VGMA1 - VGMA7
CLK1
POL
HI-Z
Y2N-1:odd number output
VGMA8 - VGMA14
Y2N:even number output
S6C1108
19
S6C1108
6 BIT 384 CHANNEL RSDS SOURCE DRIVER
RSDS DATA TIMING DIAGRAM
tHOLD2 tSETUP2 tSETUP1 tHOLD1 tSETUP1 tHOLD1
CLKP-CLKN
Input DIO: SHL=H DOI: SHL=L
D00P/N
R[0] 1
R[1] 1
R[0] 2
R[1] 2
R[0] 3
R[1] 3
R[0] 4
R[1] 4
D01P/N
R[2] 1
R[3] 1
R[2] 2
R[3] 2
R[2] 3
R[3] 3
R[2] 4
R[3] 4
D02P/N
R[4] 1
R[5] 1
R[4] 2
R[5] 2
R[4] 3
R[5] 3
R[4] 4
R[5] 4
D10P/N
G[0] 1
G[1] 1
G[0] 2
G[1] 2
G[0] 3
G[1] 3
G[0] 4
G[1] 4
D11P/N
G[2] 1
G[3] 1
G[2] 2
G[3] 2
G[2] 3
G[3] 3
G[2] 4
G[3] 4
D12P/N
G[4] 1
G[5] 1
G[4] 2
G[5] 2
G[4] 3
G[5] 3
G[4] 4
G[5] 4
D20P/N
B[0] 1
B[1] 1
B[0] 2
B[1] 2
B[0] 3
B[1] 3
B[0] 4
B[1] 4
D21P/N
B[2] 1
B[3] 1
B[2] 2
B[3] 2
B[2] 3
B[3] 3
B[2] 4
B[3] 4
D22P/N
B[4] 1
B[5] 1
B[4] 2
B[5] 2
B[4] 3
B[5] 3
B[4] 4
B[5] 4
Figure 9. RSDS Data Timing Diagram
20

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